參數(shù)資料
型號(hào)： ST7FLIT19B
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述： 8位微控制器單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，5計(jì)時(shí)器和SPI（內(nèi)部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國(guó)際檢察官聯(lián)合會(huì)的SPI的8位微控制器）
文件頁數(shù)： 66/155頁
文件大小： 2968K
代理商： ST7FLIT19B
ST7LITE1xB
66/155
1
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.6 One Pulse Mode
One pulse mode can be used to control PWM2/3
signal with an external LTIC pin. This mode is
available only in dual timer mode i.e. only for
CNTR2, when the OP_EN bit in PWM3CSR regis-
ter is set.
One Pulse mode is activated by the external LTIC
input. The active edge of the LTIC pin is selected
by the OPEDGE bit in the PWM3CSR register.
After getting the active edge of the LTIC pin,
CNTR2 is reset (000h) and PWM3 is set to high.
CNTR2 starts counting from 000h, when it reaches
the active DCR3 value then PWM3 goes low. Till
this time, any further transitions on the LTIC signal
will have no effect. If there are LTIC transistions af-
ter CNTR2 reaches DCR3 value, CNTR2 is reset
again and PWM3 goes high.
If there are no more LTIC active edges after the
first active edge then CNTR2 will count till it reach-
es the ARR2 value, and then it will be reset again
and PWM3 is set to high. The counter again starts
couting from 000h, when it reaches the active
DCR3 value PWM3 goes low, the counter counts
till it reaches ARR2, it the resets and PWM3 is set
to high and it goes on the same way.
The same operation applies for PWM2, but in this
case the comparison is done on DCR2
OP_EN and OPEDGE bits take effect on the fly
and are not synchronized with the counter 2 over-
flow.
The output bit OP2/3 can be used to inverse the
polarity of PWM2/3 in one-pulse mode. The up-
date of these bits (OP2/3) is synchronized with the
counter 2 overflow, they will be updated provided
the TRAN2 bit is set.
Notes
:
1. The time taken from activation of LTIC input and
CNTR2 reset is between 1 and 2 T
cpu
cycles, i.e.
125n to 250ns (with 8MHz f
cpu
)
2. LiteTimer input capture interrupt should be disa-
bled while 12-bit ARTimer is in One Pulse Mode.
This is to avoid spurious interrupts.
3. Priority of various conditions is as follows for
PWM3:
Break > one-pulse mode with active LTIC edge >
Forced overflow by s/w > one-pulse mode without
active LTIC edge > normal PWM operation.
4. It is possible to update DCR2/3 and OP2/3 at
the counter 2 reset, the update is synchronized
with the counter reset. This is managed by the
overflow interrupt which is generated if counter is
reset either due to ARR match or active pulse at
LTIC pin.
5. DCR2/3 and OP2/3 update in one-pulse mode
is done dynamically using force update in soft-
ware.
6. DCR3 update in this mode is not synchronized
with any event. That may lead to a longer next
PWM3 cycle duration than expected just after the
change. (refer to fig 15)
7. In one-pulse mode ATR2 value must be greater
than DCR2/3 value for PWM2/3. (opposite to nor-
mal PWM mode)
8. If there is an active edge on the LTIC pin after
the counter has reset due to an ARR2 match, then
the timer again gets reset and appears as modified
Duty cycle depending on whether the new DCR
value is less than or more than the previous value.
9. The TRAN2 bit should be set along with the
FORCE2 bit with the same instruction after a write
to the DCR register.
10. ARR2 value should be changed after an over-
flow in one pulse mode to avoid any irregular PWM
cycle.
11. When exiting from one pulse mode, the
OP_EN bit in the PWM3CSR register should be
reset first and then the ENCNTR2 bit (if counter 2
must be stopped).
How to Enter One Pulse mode:
1. Load ATR2H/ATR2L with required value.
2. Load DCR3H/DCR3L for PWM3. ATR2 value
must be greater than DCR3.
3. Set OP3 in PWM3CSR if polarity change is re-
quired.
4. Select CNTR2 by setting ENCNTR2 bit in
ATCSR2.
5. Set TRAN2 bit in ATCSR2 to enable transfer.
6. "Wait for Overflow" by checking the OVF2 flag in
ATCSR2.
7. Select counter clock using CK<1:0> bits in ATC-
SR.
8. Set OP_EN bit in PWM3CSR to enable one-
pulse mode.
9. Enable PWM3 by OE3 bit of PWMCR.
The "Wait for Overflow" in step 6 can be replaced
by forced update.
Follow the same procedure for PWM2 with the bits
corresponding to PWM2.
Note:
When break is applied in one-pulse mode,
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