參數(shù)資料
型號: ST7FLIT19B
廠商: 意法半導體
英文描述: 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述: 8位微控制器單電壓閃存存儲器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,5計時器和SPI(內(nèi)部鋼筋,鎖相環(huán),藝發(fā)局,人事,電感,國際檢察官聯(lián)合會的SPI的8位微控制器)
文件頁數(shù): 60/155頁
文件大?。?/td> 2968K
代理商: ST7FLIT19B
ST7LITE1xB
60/155
1
DUAL 12-BIT AUTORELOAD TIMER 4
(Cont’d)
11.2.3.2 Dead Time Generation
A dead time can be inserted between PWM0 and
PWM1 using the DTGR register. This is required
for half-bridge driving where PWM signals must
not be overlapped. The non-overlapping PWM0/
PWM1 signals are generated through a program-
mable dead time by setting the DTE bit.
Dead time value = DT[6:0] x Tcounter1
DTGR[7:0] is buffered inside so as to avoid de-
forming the current PWM cycle. The DTGR effect
will take place only after an overflow.
Notes:
1. Dead time is generated only when DTE=1 and
DT[6:0]
0
.
If DTE is set and DT[6:0]=0, PWM out-
put signals will be at their reset state.
2. Half Bridge driving is possible only if polarities of
PWM0 and PWM1 are not inverted, i.e. if OP0 and
OP1 are not set. If polarity is inverted, overlapping
PWM0/PWM1 signals will be generated.
3. Dead Time generation does not work at 1msec
timebase.
Figure 40. Dead Time Generation
In the above example, when the DTE bit is set:
– PWM goes low at DCR0 match and goes high at
ATR1+Tdt
– PWM1 goes high at DCR0+Tdt and goes low at
ATR match.
With this programmable delay (Tdt), the PWM0
and PWM1 signals which are generated are not
overlapped.
DCR0+1
ATR1
DCR0
T
dt
T
dt
T
dt
= DT[6:0] x T
counter1
PWM 0
PWM 1
CNTR1
CK_CNTR1
T
counter1
OVF
PWM 0
PWM 1
i
i
counter = DCR0
counter = DCR1
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