參數(shù)資料
型號: ST7FLIT19B
廠商: 意法半導(dǎo)體
英文描述: 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述: 8位微控制器單電壓閃存存儲(chǔ)器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,5計(jì)時(shí)器和SPI(內(nèi)部鋼筋,鎖相環(huán),藝發(fā)局,人事,電感,國際檢察官聯(lián)合會(huì)的SPI的8位微控制器)
文件頁數(shù): 73/155頁
文件大?。?/td> 2968K
代理商: ST7FLIT19B
ST7LITE1xB
73/155
DUAL 12-BIT AUTORELOAD TIMER 4
(Cont’d)
Bits 11:0 =
ICR[11:0]
Input Capture Data
.
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR1 register when a rising or falling edge
occurs on the ATIC or LTIC pin (depending on
ICS). Capture will only be performed when the ICF
flag is cleared.
BREAK ENABLE REGISTER (BREAKEN)
Read/Write
Reset Value: 0000 0011 (03h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 =
BREN2
Break Enable for Counter 2
This bit is read/write by software. It enables the
break functionality for Counter2 if BA bit is set in
BREAKCR. It controls PWM2/3 if ENCNTR2 bit is
set.
0: No Break applied for CNTR2
1: Break applied for CNTR2
Bit 0 =
BREN1
Break Enable for Counter 1
This bit is read/write by software. It enables the
break functionality for Counter1. If BA bit is set, it
controls PWM0/1 by default, and controls PWM2/3
also if ENCNTR2 bit is reset.
0: No Break applied for CNTR1
1: Break applied for CNTR1
TIMER CONTROL REGISTER2 (ATCSR2)
Read/Write
Reset Value: 0000 0011 (03h)
Bit 7 =
FORCE2
Force Counter 2 Overflow
This bit is read/set by software. When set, it loads
FFFh in the CNTR2 register. It is reset by hard-
ware one CPU clock cycle after counter 2 overflow
has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
Note:
This bit must not be reset by software
Bit 6 =
FORCE1
Force Counter 1 Overflow
This bit is read/set by software. When set, it loads
FFFh in CNTR1 register. It is reset by hardware
one CPU clock cycle after counter 1 overflow has
occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
Note:
This bit must not be reset by software
Bit 5 =
ICS
Input Capture Shorted
This bit is read/write by software. It allows the AT-
timer CNTR1 to use the LTIC pin for long input
capture.
0 : ATIC for CNTR1 input capture
1 : LTIC for CNTR1 input capture
Bit 4 =
OVFIE2
Overflow interrupt 2 enable
This bit is read/write by software and controls the
overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 3 =
OVF2
Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR2 register. It indicates the
transition of the counter2 from FFFh to ATR2 val-
ue.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 2 =
ENCNTR2
Enable counter2
for PWM2/3
This bit is read/write by software and switches the
PWM2/3 operation to the CNTR2 counter. If this
bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
Note:
Counter 2 gets frozen when the ENCNTR2
bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
7
0
0
0
0
0
0
0
BREN2 BREN1
7
0
FORCE
2
FORCE
1
ICS
OVFIE2
OVF2
ENCNT
R2
TRAN2 TRAN1
1
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