參數(shù)資料
型號： ST7FLIT19B
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述： 8位微控制器單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，5計時器和SPI（內(nèi)部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國際檢察官聯(lián)合會的SPI的8位微控制器）
文件頁數(shù)： 101/155頁
文件大小： 2968K
代理商： ST7FLIT19B
ST7LITE1xB
101/155
ANALOG COMPARATOR
(Cont’d)
Bit 4 =
CMPIF
Comparator Interrupt Flag
This bit is set by hardware when interrupt is gener-
ated at the rising edge (CINV = 0) or falling edge
(CINV = 1) of comparator output. This bit is
cleared by reading the CMPCR register. Writing to
this bit does not change the value.
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate
interrupt if CMPIE is set.
Bit 3 :
CMPIE
Comparator Interrupt Enable
This bit is set or reset by software and cleared by
hardware reset. This bit enables or disables the in-
terrupt generation depending on interrupt flag
0: Interrupt not generated
1: Interrupt generated if interrupt flag is set
Note:
This bit should be set to enable interrupt only after
the comparator has been switched ON, i.e. when
CMPON is set.
Once CMPON bit is set, it is recommended to wait
the specified stabilisation time before setting
CMPIE bit in order to avoid a spurious interrupt
(see
section 13.12 on page 140
).
Bit 2 :
CMP
Comparator Output
This bit is set or reset by software and cleared by
hardware reset. It stores the value of comparator
output.
Bit 1 =
COUT
Comparator Output Enable on Port
This bit is set or cleared by software. When this bit
is set, the comparator output is available on PA7
port.
0 : Comparator output not connected to PA7
1 : Comparator output connected to PA7
Bit 0 :
CMPON
Comparator ON/OFF
This bit is set or cleared by software and reset by
hardware reset. This bit is used to switch ON/OFF
the comparator, internal voltage reference and
current bias which provides 4μA current to both.
0: Comparator, Internal Voltage Reference, Bias
OFF (in power-down state).
1: Comparator, Internal Voltage Reference, Bias
ON
Note:
For the comparator interrupt generation, it
takes 250ns delay from comparator output change
to rising or falling edge of interrupt generated.
Table 21. Analog Comparator Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
002Ch
VREFCR
Reset Value
VCEXT
0
VCBGR
0
VR3
0
VR2
0
VR1
0
VR0
0
-
0
-
0
002Dh
CMPCR
Reset value
CHYST
1
-
0
CINV
0
CMPIF
0
CMPIE
0
CMP
0
COUT
0
CMPON
0
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