參數(shù)資料
型號(hào)： ST7FLIT19B
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述： 8位微控制器單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，5計(jì)時(shí)器和SPI（內(nèi)部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國際檢察官聯(lián)合會(huì)的SPI的8位微控制器）
文件頁數(shù)： 72/155頁
文件大?。?/td> 2968K
代理商： ST7FLIT19B
ST7LITE1xB
72/155
1
DUAL 12-BIT AUTORELOAD TIMER 4
(Cont’d)
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
BRSEL
Break Input Selection
This bit is read/write by software and cleared by
hardware after reset. It selects the active Break
signal from external BREAK pin and the output of
the comparator.
0: External BREAK pin is selected for break mode.
1: Comparator output is selected for break mode.
Bit 6 =
BREDGE
Break Input Edge Selection
This bit is read/write by software and cleared by
hardware after reset. It selects the active level of
Break signal.
0: Low level of Break selected as active level.
1: High level of Break selected as active level.
Bit 5 =
BA
Break Active.
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the ac-
tive level defined by the BREDGE bit is applied on
the BREAK pin. It activates/deactivates the Break
function.
0: Break not active
1: Break active
Bit 4 =
BPEN
Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
0: Break pin disabled
1: Break pin enabled
Bits 3:0 =
PWM[3:0]
Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active and correspond-
ing OEx bit is set.
PWMx DUTY CYCLE REGISTER HIGH
(DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
PWMx DUTY CYCLE REGISTER LOW
(DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 =
DCRx[11:0]
PWMx Duty Cycle Value
This 12-bit value is written by software. It defines
the duty cycle of the corresponding PWM output
signal (see
Figure 38
).
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see
Figure 38
). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
7
0
BRSEL BREDGE
BA
BPEN
PWM3
PWM2
PWM1 PWM0
15
8
0
0
0
0
DCR11 DCR10 DCR9
DCR8
7
0
DCR7
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
15
8
0
0
0
0
ICR11 ICR10
ICR9
ICR8
7
0
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
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