參數(shù)資料
型號(hào): ST7FLIT19B
廠(chǎng)商: 意法半導(dǎo)體
英文描述: 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述: 8位微控制器單電壓閃存存儲(chǔ)器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,5計(jì)時(shí)器和SPI(內(nèi)部鋼筋,鎖相環(huán),藝發(fā)局,人事,電感,國(guó)際檢察官聯(lián)合會(huì)的SPI的8位微控制器)
文件頁(yè)數(shù): 70/155頁(yè)
文件大?。?/td> 2968K
代理商: ST7FLIT19B
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ST7LITE1xB
70/155
1
DUAL 12-BIT AUTORELOAD TIMER 4
(Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = Reserved.
Bit 6 =
ICF
Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 =
ICIE
IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
Bits 4:3 =
CK[1:0]
Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Bit 2 =
OVF1
Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter1 CNTR1 from FFFh to
ATR1 value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 =
OVFIE1
Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 0 =
CMPIE
Compare Interrupt Enable
.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled.
1: Output Compare interrupt enabled.
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (00h)
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 =
CNTR1[11:0]
Counter Value
.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter CNTR1 in-
crements continuously as soon as a counter clock
is selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. As there is no latch, it is recom-
mended to read LSB first. In this case, CNTR1H
can be incremented between the two read opera-
tions and to have an accurate result when
f
timer
=f
CPU
, special care must be taken when
CNTR1L values close to FFh are read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
7
0
0
ICF
ICIE
CK1
CK0
OVF1 OVFIE1 CMPIE
Counter Clock Selection
CK1
CK0
OFF
32MHz
0
1
0
1
0
1
1
0
f
LTIMER
(1 ms timebase @ 8 MHz)
f
CPU
15
8
0
0
0
0
CNTR1_
11
CNTR1_
10
CNTR1_
9
CNTR1_
8
7
0
CNTR1_
7
CNTR1_
6
CNTR1_
5
CNTR1_
4
CNTR1_
3
CNTR1_
2
CNTR1_
1
CNTR1_
0
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