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參數(shù)資料
| 型號： | ST7FLIT19B |
| 廠商： | 意法半導體 |
| 英文描述： | 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU) |
| 中文描述： | 8位微控制器單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，5計時器和SPI（內(nèi)部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國際檢察官聯(lián)合會的SPI的8位微控制器） |
| 文件頁數(shù)： | 34/155頁 |
| 文件大小： | 2968K |
| 代理商： | ST7FLIT19B |
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ST7LITE1xB
34/155
1
SYSTEM INTEGRITY MANAGEMENT
(Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 0110 0xx0 (6xh)
Bit 7 =
LOCK32
PLL 32Mhz Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL 32Mhz reaches its oper-
ating frequency
0: PLL32 not locked
1: PLL32 locked
Bits 6:5 =
CR[1:0]
RC Oscillator Frequency Ad-
justment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain an
accuracy of 1%. Refer to
section 7.3 on page 25
.
Bit 4 =
WDGRF
Watchdog Reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 =
LOCKED
PLL
Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
Bit 2 =
LVDRF
LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 1 =
AVDF
Voltage Detector Flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to
Figure
20
and to
Section 7.6.2.1
for additional details.
0: V
DD
over AVD threshold
1: V
DD
under AVD threshold
Bit 0 =
AVDIE
Voltage Detector Interrupt Enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
PLL TEST REGISTER (PLLTST)
Read/Write
Reset Value: 0000 0000(00h)
Bit 7 :
PLLdiv2
PLL clock divide by 2
This bit is read or write by software and cleared by
hardware after reset. This bit will divide the PLL
output clock by 2.
0 : PLL output clock
1 : Divide by 2 of PLL output clock
Refer “Clock Management Block Diagram” on
page 26
Note :
Write of this bit will be effective after 2 Tcpu
cycles (if system clock is 8mhz) else 1 cycle (if
system clock is 4mhz) i.e. effective time is 250ns.
Bit 6:0 : Reserved , Must always be cleared
7
0
LOCK
32
CR1 CR0
WDG
RF
LOCKED LVDRF AVDF AVDIE
RESET Sources
LVDRF
WDGRF
External RESET pin
Watchdog
LVD
0
0
1
0
1
X
7
0
PLLdiv2
0
0
0
0
0
0
0
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