參數(shù)資料
型號： ST7FLIT19B
廠商： 意法半導體
英文描述： 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述： 8位微控制器單電壓閃存存儲器，數(shù)據(jù)EEPROM，模數(shù)轉換器，5計時器和SPI（內部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國際檢察官聯(lián)合會的SPI的8位微控制器）
文件頁數(shù)： 28/155頁
文件大?。?/td> 2968K
代理商： ST7FLIT19B
ST7LITE1xB
28/155
1
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
Figure 16
:
■
External RESET source pulse
■
Internal LVD RESET (Low Voltage Detection)
■
Internal WATCHDOG RESET
Note:
A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
section 12.2.1 on page 105
for further de-
tails.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
Figure 15
:
■
Active Phase depending on the RESET source
■
256 or 4096 CPU clock cycle delay (see table
below)
■
RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically select-
ed depending on the clock source chosen by op-
tion byte:
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
STARTUP
(see
Figure 13
).
Figure 15. RESET Sequence Phases
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
ON
weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized (see
Figure 17
). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Figure 16. Reset Block Diagram
Clock Source
CPU clock
cycle delay
256
256
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
4096
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
RESET
R
ON
V
DD
WATCHDOG RESET
ILLEGAL OPCODE RESET
1)
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
Filter
Note 1
: See “Illegal Opcode Reset” on page 105. for more details on illegal opcode reset conditions.
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ST7FLIT19BF0MX 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
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