參數(shù)資料
型號(hào): ST7FLIT19B
廠商: 意法半導(dǎo)體
英文描述: 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述: 8位微控制器單電壓閃存存儲(chǔ)器,數(shù)據(jù)EEPROM,模數(shù)轉(zhuǎn)換器,5計(jì)時(shí)器和SPI(內(nèi)部鋼筋,鎖相環(huán),藝發(fā)局,人事,電感,國際檢察官聯(lián)合會(huì)的SPI的8位微控制器)
文件頁數(shù): 29/155頁
文件大小: 2968K
代理商: ST7FLIT19B
ST7LITE1xB
29/155
RESET SEQUENCE MANAGER
(Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.5.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
DD
is over the minimum
level specified for the selected f
OSC
frequency.
A proper reset signal for a slow rising V
DD
supply
can generally be provided by an external RC net-
work connected to the RESET pin.
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
Power-On RESET
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V
DD
<V
IT+
(rising edge) or
V
DD
<V
IT-
(falling edge) as shown in
Figure 17
.
The LVD filters spikes on V
DD
larger than t
g(VDD)
to
avoid parasitic resets.
7.5.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Figure 17
.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
Figure 17. RESET Sequences
V
DD
RUN
RESET PIN
EXTERNAL
RESET
SOURCE
WATCHDOG
RESET
ACTIVE PHASE
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
RUN
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN
RUN
EXTERNAL
RESET
LVD
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 T
CPU
)
VECTOR FETCH
ACTIVE
PHASE
ACTIVE
PHASE
1
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