參數(shù)資料
型號(hào)： ST7FLIT19B
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU With Single Voltage Flash Memory, Data EEPROM, ADC, 5 Timers, SPI(內(nèi)部RC,PLL,ADC,ROP,ICP, IAP,SPI的8位MCU)
中文描述： 8位微控制器單電壓閃存存儲(chǔ)器，數(shù)據(jù)EEPROM，模數(shù)轉(zhuǎn)換器，5計(jì)時(shí)器和SPI（內(nèi)部鋼筋，鎖相環(huán)，藝發(fā)局，人事，電感，國際檢察官聯(lián)合會(huì)的SPI的8位微控制器）
文件頁數(shù)： 54/155頁
文件大?。?/td> 2968K
代理商： ST7FLIT19B
ST7LITE1xB
54/155
1
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
■
Programmable free-running downcounter (64
increments of 16000 CPU cycles)
■
Programmable reset
■
Reset (if watchdog activated) when the T6 bit
reaches zero
■
Optional
(configurable by option byte)
■
Hardware Watchdog selectable by option byte
reset
on
HALT
instruction
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30μs.
Figure 34. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
f
CPU
T6
T0
CLOCK DIVIDER
÷
16000
WATCHDOG CONTROL REGISTER (CR)
T1
T2
T3
T4
T5
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