參數(shù)資料
型號： ST72331
廠商： 意法半導體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計時器（8位微控制器（8米））
文件頁數(shù)： 67/98頁
文件大?。?/td> 1123K
代理商： ST72331
67/98
ST72331
SERIAL PERIPHERAL INTERFACE
(Cont’d)
4.6.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 41
, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 40
).
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
This pin must be toggled high and low between
each byte transmitted (see
Figure 40
).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 41. CPHA / SS Timing Diagram
MOSI/MISO
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131C
129
相關PDF資料
PDF描述
ST72371 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
ST72372 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
ST72681 USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER
ST72753L4 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C
ST72753L5 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C
相關代理商/技術參數(shù)
參數(shù)描述
ST72331J2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT MICROCONTROLLER (MCU) WITH 8/16K ROM/OTP/EPROM.256 EEPROM.384/512 BYTES RAM.ADC.WDG.SCI.SPI & 2 TIMERS - SDIP42/56. QFP44/64
ST72331J2B1/XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
ST72331J2B6/XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
ST72331J2T1/XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
ST72331J2T6/XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*