參數(shù)資料
型號(hào)： ST72331
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲(chǔ)器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計(jì)時(shí)器（8位微控制器（8米））
文件頁(yè)數(shù)： 24/98頁(yè)
文件大?。?/td> 1123K
代理商： ST72331
24/98
ST72331
3.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
Register Address: 0020h
Reset Value: 0000 0000 (00h)
—
Read/Write
Bit 7:6 =
PEI[3:2]
External Interrupt EI3 and EI2
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to
Table 7
.
Table 7. EI2 and EI3 External Interrupt Polarity
Options
Bit 5 =
MCO
Main Clock Out
This bit is set and cleared by software. When set it
allows to output the Internal Clock on PF0 I/O.
0 - PF0 is a normal I/O port.
1 - f
CPU
outputs on PF0 pin.
Bit 4:3 =
PEI1-PEI0
External Interrupt EI1 and EI0
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to
Table 8
.
Table 8. EI0 and EI1 External Interrupt Polarity
Options
Bit 2:1 =
PSM[1:0]
Prescaler for Slow Mode
These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.
Table 9. f
CPU
Value in Slow Mode
Bit 0 =
SMS
Slow Mode Select
This bit is set and cleared by software.
0: Normal Mode - f
CPU
= f
OSC
/ 2
(Reset state)
1: Slow Mode - the f
CPU
value is determined by the
PSM1 and PSM0 bits.
7
0
PEI3 PEI2 MCO PEI1 PEI0
PSM1
PSM0
SMS
MODE
PEI3
PEI2
Falling edge and low level
(Reset state)
Falling edge only
Rising edge only
Rising and falling edge
0
0
1
0
1
0
1
1
MODE
PEI1
PEI0
Falling edge and low level
(Reset state)
Falling edge only
Rising edge only
Rising and falling edge
0
0
1
0
1
0
1
1
f
CPU
Value
f
OSC
/ 4
f
OSC
/ 16
f
OSC
/ 8
f
OSC
/ 32
PSM1
0
0
1
1
PSM0
0
1
0
1
86
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