參數(shù)資料
型號： ST72331
廠商： 意法半導體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計時器（8位微控制器（8米））
文件頁數(shù)： 36/98頁
文件大?。?/td> 1123K
代理商： ST72331
36/98
ST72331
WATCHDOG TIMER
(Cont’d)
4.3.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see
Table 13
):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Table 13. Watchdog Timing (f
CPU
= 8 MHz)
Notes:
Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
4.3.4 Hardware Watchdog Option
If Hardware Watchdog Is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Refer to the device-specific Option Byte descrip-
tion.
4.3.5 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 =
WDGA
Activation bit
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note:
This bit is not used if the hardware watch-
dog otion is enabled by option byte.
Bit 6-0 =
T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
become cleared).
STATUS REGISTER (SR)
Read/Write
Reset Value*: 0000 0000 (00h)
Bit 0 =
WDOGF
Watchdog flag
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred
* Only by software and power on/off reset
Note:
This register is not used in versions without
LVD Reset.
Table 14. WDG Register Map
CR Register
initial value
FFh
C0h
WDG timeout period
(ms)
98.304
1.536
Max
Min
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
7
0
-
-
-
-
-
-
-
WDOGF
Address (Hex.)
Register Name
7
6
5
4
3
2
1
0
2A
CR
WDGA
T6.. T0
2B
SR
-
-
-
-
-
-
-
WDOGF
98
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