參數(shù)資料
型號： ST72331
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計(jì)時(shí)器（8位微控制器（8米））
文件頁數(shù)： 10/98頁
文件大?。?/td> 1123K
代理商： ST72331
10/98
ST72331
Table 4. Hardware Register Memory Map
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h to
001Fh
0020h
0021h
0022h
0023h
0024h to
0029h
002Ah
002Bh
002Ch
002Dh to
0030h
Port A
PADR
PADDR
PAOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W
1)
Reserved Area (1 byte)
Port C
PCDR
PCDDR
PCOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W
Reserved Area (1 byte)
Port B
PBDR
PBDDR
PBOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W
1)
Reserved Area (1 byte)
Port E
PEDR
PEDDR
PEOR
Data Register
Data Direction Register
Option Register
00h
00h
0Ch
R/W
R/W
R/W
1)
Reserved Area (1 byte)
Port D
PDDR
PDDDR
PDOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W
1)
Reserved Area (1 byte)
Port F
PFDR
PFDDR
PFOR
Data Register
Data Direction Register
Option Register
00h
00h
28h
R/W
R/W
R/W
1)
Reserved Area (9 bytes)
MISCR
SPIDR
SPICR
SPISR
Miscellaneous Register
SPI Data I/O Register
SPI Control Register
SPI Status Register
00h
xxh
xxh
00h
SPI
R/W
R/W
Read Only
Reserved Area (6 bytes)
WDG
WDGCR
WDGSR
EEPCR
Watchdog Control Register
Watchdog Status Register
EEPROM Control Register
7Fh
00h
00h
R/W
R/W
3)
R/W Register
EEPROM
Reserved Area (4 bytes)
72
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