參數(shù)資料
型號： ST72331
廠商： 意法半導體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計時器（8位微控制器（8米））
文件頁數(shù)： 60/98頁
文件大?。?/td> 1123K
代理商： ST72331
60/98
ST72331
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: Undefined
Bit 7 =
R8
Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 =
T8
Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 4 =
M
Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 3 =
WAKE
Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
TIE
Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 6 =
TCIE
Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SR register
Bit 5 =
RIE
Receiver interrupt enable
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
Bit 4 =
ILIE
Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 3 =
TE
Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
1: Transmitter is enabled
Note:
during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 2 =
RE
Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
Bit 1 =
RWU
Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 0 =
SBK
Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note:
If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
7
0
R8
T8
-
M
WAKE
-
-
-
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
122
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