參數(shù)資料
型號(hào)： ST72331
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲(chǔ)器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計(jì)時(shí)器（8位微控制器（8米））
文件頁(yè)數(shù)： 37/98頁(yè)
文件大小： 1123K
代理商： ST72331
37/98
ST72331
4.4 16-BIT TIMER
4.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compareand PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
4.4.2 Main Features
I
Programmable prescaler: f
CPU
divided by 2, 4 or 8.
I
Overflow status flag and maskable interrupt
I
External clock input (must be at least 4 times
slower than the CPU
clock speed) with the choice
of active edge
I
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Pulse width modulation mode (PWM)
I
One pulse mode
I
5 alternate functions on I/O ports*
The Block Diagram is shown in
Figure 1
.
*Note:
Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
4.4.3 Functional Description
4.4.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Table 1
. The
value in the counter register repeats every
131.072, 262.144 or 524.288 internal processor
clock cycles depending on the CC1 and CC0 bits.
99
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