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參數(shù)資料
| 型號： | ST72331 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M)) |
| 中文描述： | 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計時器（8位微控制器（8米）） |
| 文件頁數(shù)： | 47/98頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | ST72331 |
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ST72331
16-BIT TIMER
(Cont’d)
4.4.4 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
Bit 7 =
ICIE
Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 =
OCIE
Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 =
TOIE
Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 4 =
FOLV2
Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin.
Bit 3 =
FOLV1
Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin.
Bit 2 =
OLVL2
Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 =
IEDG1
Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 =
OLVL1
Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
109
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