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參數(shù)資料
| 型號： | ST72331 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M)) |
| 中文描述： | 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計時器（8位微控制器（8米）） |
| 文件頁數(shù)： | 41/98頁 |
| 文件大小： | 1123K |
| 代理商： | ST72331 |
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ST72331
16-BIT TIMER
(Cont’d)
4.4.3.3 Input Capture
In this section, the index, i may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPipin (see figure 5).
ICi Rregister is a read-only register.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (
f
CPU
/(CC1.CC0)
).
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC1-CC0) (see
Table 1
).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When an input capture occurs:
– ICFibit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see
Figure 6
).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request is
done in two steps:
1. Reading the SR register while the ICFibit is set.
2. An access (read or write) to the ICiLR register.
Note:
After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR regis-
ter is also read.
The ICiR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
During HALT mode, if at least one valid input cap-
ture edge occurs on the ICAPipin, the input cap-
ture detection circuitry is armed. This does not set
any timer flags, and does not “wake-up” the MCU.
If the MCU is awoken by an interrupt, the input
capture flag will become active, and data corre-
sponding to the first valid edge during HALT mode
will be present.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
103
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