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參數(shù)資料
| 型號： | ST72331 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M)) |
| 中文描述： | 8位微控制器與8至16K的光碟/雙層/存儲器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計時器（8位微控制器（8米）） |
| 文件頁數(shù)： | 43/98頁 |
| 文件大?。?/td> | 1123K |
| 代理商： | ST72331 |
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43/98
ST72331
16-BIT TIMER
(Cont’d)
4.4.3.4 Output Compare
In this section, the index, i may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
i
R value to 8000h.
Timing resolution is one count of the free running
counter: (
f
CPU/(CC1.CC0)
).
Procedure
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPipin is dedicated to the output compare i
function.
– Select the timer clock (CC1-CC0) (see
Table 1
).
And select the following in the CR1 register:
– Select the OLVLibit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When match is found:
– OCFi bit is set.
– The OCMPipin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
Clearing the output compare interrupt request is
done by:
3. Reading the SR register while the OCFi bit is
set.
4. An access (read or write) to the OCiLR register.
Note:
After a processor write cycle to the OCiHR
register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
The value in the 16-bit OC
i
R egister and the OLVi
bit should be changed after each successful com-
parison in order to control an output waveform or
establish a new elapsed timeout.
When the clock is divided by 2, OCFiand OCMPi
are set while the counter value equals the OCiR
register value (see
Figure 8
). This behaviour is the
same in OPM or PWM mode.
When the clock is divided by 4, 8 or in external
clock mode , OCFiand OCMPiare set while the
counter value equals the OCiR register value plus
1 (see
Figure 9
).
The OC
i
R register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t
= Desired output compare period (in
seconds)
= Internal clock frequency
= Timer clock prescaler (CC1-CC0 bits,
see
Table 1
)
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OC
i
R register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
f
CPU
t
PRESC
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
t
*
f
CPU
t
PRESC
105
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