參數(shù)資料
型號(hào)： ST72331
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCU with 8 to 16K ROM/OTP/EPROM, 256 EEPROM, 384 to 512 Bytes RAM, ADC, WDG, SCI, SPI and 2 Timers(8位微控制器(8M))
中文描述： 8位微控制器與8至16K的光碟/雙層/存儲(chǔ)器，256的EEPROM，384字節(jié)RAM為512，藝發(fā)局，水分散粒劑，脊髓損傷，SPI和2計(jì)時(shí)器（8位微控制器（8米））
文件頁(yè)數(shù)： 65/98頁(yè)
文件大?。?/td> 1123K
代理商： ST72331
65/98
ST72331
SERIAL PERIPHERAL INTERFACE
(Cont’d)
4.6.4 Functional Description
Figure 38
shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in
Section
4.6.5
for the bit definitions.
4.6.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see
Figure 41
).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is writ-
ten in the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A write or a read of the DR register.
Note:
While the SPIF bit is set, all writes to the DR
127
相關(guān)PDF資料
PDF描述
ST72371 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
ST72372 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
ST72681 USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER
ST72753L4 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C
ST72753L5 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST72331J2 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-BIT MICROCONTROLLER (MCU) WITH 8/16K ROM/OTP/EPROM.256 EEPROM.384/512 BYTES RAM.ADC.WDG.SCI.SPI & 2 TIMERS - SDIP42/56. QFP44/64
ST72331J2B1/XXX 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller
ST72331J2B6/XXX 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller
ST72331J2T1/XXX 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller
ST72331J2T6/XXX 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:8-Bit Microcontroller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*