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參數(shù)資料
| 型號： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁數(shù)： | 51/66頁 |
| 文件大?。?/td> | 917K |
| 代理商： | SPEAR-09-B042 |
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SPEAR-09-B042
Standard customization
9.4.12
Interrupt and DMA request management
This IP collects the interrupt request of several IPs in order to merge them on the intrrupt0
line of the interrupt controller. The interrupt handler that must determine the root of the
interrupt.
The IPs using interrupt0 line are the following:
●
Keyboard,
●
Legacy GPIOs,
●
GPIO_IT bus,
●
I2S,
●
TDM,
●
Camera interface.
The IP is also connected on DMA_REQ channels 2 to 4 and transmits the request from the
following IPs:
●
I2S,
●
TDM,
●
Camera interface.
DMA requests can be DMA burst request and/or DMA single request.
Events of the different IPs able to generate an interrupt are the following:
●
Keyboard,
●
Legacy GPIOs,
●
IT_GPIO persistent change supervision,
●
IT_GPIO change supervision,
●
I2S buffer bank switching,
●
TDM buffer bank switching,
●
Camera interface new line available,
●
Camera interface end of frame,
●
Camera interface vertical sync appears active.
The following types of IP DMA requests are supported:
●
I2S buffer bank switching,
●
TDM buffer bank switching,
●
Camera interface new line available.
Table 21.
Camera interface timing specification
Symbol
Description
Min
Max
Unit
fPCLK
PCLK frequency
100
MHz
tPCLKL
PCLK low width
1/fPCLK - 3
1/fPCLK + 3
ns
tPCLKH
PCLK high width
1/fPCLK - 3
1/fPCLK + 3
ns
tDV
PCLK to data
-3
3
ns
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| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
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