參數(shù)資料
型號(hào): SPEAR-09-B042
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289
封裝: 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289
文件頁(yè)數(shù): 42/66頁(yè)
文件大?。?/td> 917K
代理商: SPEAR-09-B042
SPEAR-09-B042
Standard customization
Figure 10.
Switching constant delay between TSy and TSx
Note:
The last timeslot of a frame can be played in the first timeslot of the next frame.
TDM timeslot bufferization
Bufferization means that data from DIN is stored in an input buffer and data from an output
buffer is played on DOUT. When the number of sample stored/played reaches the buffer
size, the processor is interrupted in order to read the input buffer and prepare a new output
buffer (or a DMA request is raised).
Up to 16 channels can be stored or played. It is not mandatory that an input-bufferized
channel is also output bufferized (it can be switched or high impedance).
Channels can contain one byte (timeslot) when the data is companded, two bytes when the
data is either stereo companded or mono linear (16-bits) or four bytes when the data is
stereo linear. The timeslots need not be successive, but must be byte aligned.
When using 16 channels, 512 ms buffers can be used for stereo linear mode. Using 8, 4, 2
or 1 channel increases the buffer size to 1024, 2048, 4096 or 8192 ms (always for stereo
linear mode). If data is on two bytes per frame, the values are doubled. If data is mono
companded the data are multiplied by four.
All the channels must have the same buffer size. Thus if a vocoder for one channel requires
30 ms packets, and another channel requires 20 ms, a 10 ms buffer must be created, and
DMA used to generate the voice packet in the DDR.
Oherwise, if all the channels require the same packet size, the data can be directly
computed inside the buffer and do not need to be transferred to DDR. The only constraint is
to maintain operation the real time.
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