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參數(shù)資料
| 型號(hào)： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁(yè)數(shù)： | 41/66頁(yè) |
| 文件大小： | 917K |
| 代理商： | SPEAR-09-B042 |
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Standard customization
SPEAR-09-B042
The following pre-defined shapes are available:
●
short frame narrow-band delayed and non delayed
●
short frame wide-band delayed and non delayed
●
I2S or serial aligned long frame.
Figure 9.
Pre-defined frame sync shapes (slave or master)
SYN4 to SYNC7 are generated from the sync memory. The sync memory has 1024 words
per four bytes. Byte0 of each location is used to generate SYNC4. Byte1 for SYNC5, Byte2
for SYNC6 and Byte3 for SYNC7. The MSB of each byte is issued first. The LSB is issued
the last. This covers the 1024 possible time slots for the four sync signals.
TDM timeslot switching
Any of the output time slots can receive any input timeslot of the previous frame. The
connection memory is part of the action memory, informing which timeslot has to be output.
The data memory contains two banks. One storing the actual frame from the DIN pin (if
switching has been validated for this timeslot in the action memory), the other outputting the
data from the previous frame on DOUT (if the switching has been validated and high
impedance bit is not set in the action memory).
The delay between out_TSy receiving IN_TSx for a TDM containing N+1 timeslots is
constant:
Delay(TS)= y + (N+1- x)
with x and y between 0 and N.
Figure 10 shows an example with N+1 = 32.
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| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
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