參數(shù)資料
型號： SPEAR-09-B042
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289
封裝： 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289
文件頁數(shù)： 47/66頁
文件大?。?/td> 917K
代理商： SPEAR-09-B042
SPEAR-09-B042
Standard customization
DAC performances
9.4.10
ADC enhanced control
The ADC is a 10-bit, 8 channel cell described in Section 8.14.
In order to synchronize the TDM or the DAC and the ADC, there is a mechanism allowing
channel 0 to be controlled by the TDM clock.
The ADC sampling rate can be adjusted from the sync frequency (generally 8 kHz), up to
TDM CLK frequency. For example, if the SYNC signal is at 8 kHz and the CLK signal is at
2048, the ADC sampling can be requested every 2-bits, leading to an over sampling of 128.
In this case the resolution of the ADC is increased to 13.5-bits.
9.4.11
Camera interface
The camera interface recieves data from a sensor in parallel mode (8 to 14-bits) by storing a
full line in a buffer memory, then requesting a DMA transfer or interrupting the processor.
When all the lines of a frame are transferred, a frame sync interrupt is generated.
The camera interface accepts both hardware synchronization (HSYNC and VSYNC signals)
or embedded synchros (ITU656 or CSI2).
Figure 12, Figure 13, Figure 14, Figure 15 shows the three possible synchronizations:
Figure 12.
External HSYNC synchronization
Table 18.
DAC performances
Symbol
Min
Typ
Max
Input bits
32
oversampling
32
256
S/N ratio
82 dB (1)
1.
Measured on a 1 kHz sine wave *64 over sampled by the processor and *32 by the DAC.
THD
72 dB (1)
dynamic
80% of full scale
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