參數(shù)資料
型號(hào)： SPEAR-09-B042
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289
封裝： 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289
文件頁(yè)數(shù)： 46/66頁(yè)
文件大?。?/td> 917K
代理商： SPEAR-09-B042
Standard customization
SPEAR-09-B042
The SPI extension is made by generating three more slave select signals SS1, SS2 and
SS3.
The I2C extension is done by repeating the I2C_SCL signal if the considered pin is set
active.
Otherwise the pin remains low, so that the start condition is not met.
Each of the 8 pins can reproduce either the SPI SS0 signal, or the I2C I2C_SCL signal. The
selection is made through a register.
9.4.8
GPIO_IT cell
GPIO_IT is an 8-bit supervised input bus. It can be programmed to generate a change
interrupt (ITch) when a change is detected on any of the eight bus signals. If it is important
that the change persists for more than a determined time before an interrupt is generated, a
'persist' interrupt (ITp) can be programmed.
The signal is latched twice, and the two latched signals are compared. If they are different,
an ITch interrupt is generated if the line is programmed to generate a change interrupt (and
it is not masked). The programmer can then read both the first and the second latch
registers.
The number of clocks before validating a persistent change is programmable. An ITp
interrupt is generated if the line is programmed to generate a persist interrupt (and it is not
masked). When the persistency counter reaches the persistence time, the data is latched
and the programmer can read the latched data.
This interface is principally intended for supervision of the hook detection of up to 8 SLICs.
However it is also useful for switch debouncing and simple interrupt generation when a
signal toggles.
The GPIO_IT interface is clocked by the TDM clock.
9.4.9
One bit DAC
The one-bit DAC is a second-order noise shaper based on the TDM hardware. The action
memory determines whether a new sample needs to be sent to the DAC during the next
byte. Samples are read from the buffer memory.
Input data must be 32-bits wide, either in 2’s complement or binary form.
Optionally, the order of the noise shaper can be set to 1.
Operation without using the TDM
DAC cell is capable of operating without using the TDM. In this case, the input data can be
over sampled by the processor then over sampled by the DAC by a factor between 32 and
256. For example, 64 kHz over sampled data leads to a 2048 kHz output waveform when
the DAC over sampling factor is set to 32.
Operation in conjunction with the TDM
When used in conjunction with the TDM, a bufferization channel must be reserved for the
DAC. In this case the input sampling frequency must be either 8 kHz (standard TDM) or 16
kHz (when connecting wide-band CODECs for instance). The number of bits in a frame
must be fixed between 32 and 256, leading to an over-sampling factor of 32 to 256. For
example an 8 kHz input and a 256-bit frame generates a 2048 kHz output.
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