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參數(shù)資料
| 型號(hào)： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 917K |
| 代理商： | SPEAR-09-B042 |
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SPEAR-09-B042
Standard customization
9.4.5
TDM interface
The TDM block implements time division multiplexing with up to 1024 time slots. It uses 11
pins.
The TDM interface can be the master or a slave of the CLK or SYNC0 signals.
It is a master when generating SYNC1 to SYNC7, which are seven additional sync signals
for devices that do not recognize time slots, or which need a special synchronization
waveform.
DIN receives the data.
DOUT transmits the data. This line can be high impedance on timeslot not used.
Timeslots can be used in two ways: switching or bufferization. The information about
timeslot usage is written in a 1024*32 memory, termed the 'action memory'. Switching and
bufferization can be used concurrently for different timeslots on the same TDM. The only
limitation is that an output timeslot can not be switched and bufferized at the same time.
Clock signal: device can be master or slave.
In master mode the CLK signal can be generated from different sources:
●
ClkR_Osci1: MCLK clock from external MCLK crystal
●
ClkR_Gpio4: external oscillator from PL_CLK4 pin.
●
ClkR_Synt_3: From frequency synthetiser (source is AHB frequency).
All three signals can be divided by the TDM_CLK block in order to obtain the correct
frequency.
In slave mode, the clock is received on the TDM_CLK pin.
The clock used internally is present on the PL_CLK pins.
Sync signal: device can be master or slave.
SYNC0 can be master or slave. SYNC1 to SYNC7 are additional generated synchro
dedicated to devices that does not recognize the timeslots orwhich need special waveforms.
SYNC1 to SYNC3 are built from SYNC0.
Sync0 in slave and master mode and Sync1 to Sync3 support several pre-defined wave
shapes.
SYNC4 to SYNC7 are generated using the SYNC memory (1024*32) where each bit is set
to 0 or 1 to generate the right pattern on the pin during a frame.
Table 16.
TDM block pins
Pins
Description
SYNC7-0
Dedicated frame synchro for CODECs without timeslot recognition
CLK
TDM clock
DIN
TDM input
DOUT
TDM output (tri-state)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
| SPEAR-09-H022_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC |
| SPEAR-09-H042 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head200, ARM 926, 200 K customizable eASIC⑩ gates, large IP portfolio SoC |
| SPEAR-09-H122 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
| SPEAR-09-H122_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
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