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參數(shù)資料
| 型號： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁數(shù)： | 38/66頁 |
| 文件大小： | 917K |
| 代理商： | SPEAR-09-B042 |
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SPEAR-09-B042
Standard customization
Key features
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Meets SD host controller standard specification version 2.0
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Meets SDIO card specification version 2.0
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Meets SD memory card specification draft version 2.0
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Meets SD memory card security specification version 1.01
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Meets MMC specification version 3.31 and 4.2
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Supports both DMA and Non-DMA mode of operation
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Supports MMC plus and MMC mobile
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Card detection (insertion/removal)
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Password protection of cards
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Host clock rate variable between 0 and 52 MHz
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Supports 1-bit, 4-bit and 8-bit SD modes and SPI mode
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Supports MultiMediaCard interrupt mode
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Allows card to interrupt host in 1-bit, 4-bit, 8-bit SD modes and SPI mode.
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Up to 100 Mbit/s data rate using 4 parallel data lines (sd4-bit mode)
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Up to 416 Mbit/s data rate using 8-bit parallel data lines (sd8-bit mode)
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Cyclic redundancy check CRC7 for command and CRC16 for data integrity
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Designed to work with I/O cards, read-only cards and read/write cards
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Error correction code (ECC) support for MMC4.2 cards
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Supports read wait control, suspend/resume operation
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Supports FIFO overrun and Under run condition by stopping the SD clock
9.4.3
Flexible static memory controller
Main features of the FSMC are listed below:
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Provides an interface between AHB system bus and external parallel memory devices.
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Interfaces static memory-mapped devices including RAM, ROM and synchronous burst
Flash.
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For SRAM, ROM and Flash 8/16-bit wide, external memory and data paths are
provided.
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FSMC performs only one access at a time and only one external device is accessed.
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Little-endian and big-endian memory architectures.
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AHB burst transfer handling to reduce access time to external devices.
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Supplies an independent configuration for each memory bank.
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Programmable timings to support a wide range of devices.
–
Programmable wait states (up to 31).
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Programmable bus turnaround cycles (up to 15).
–
Programmable output enable and write enable delays (up to 15).
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Independent chip select control for each memory bank.
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Shares the address bus and the data bus with all the external peripherals.
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Only chips selects are unique for each peripheral.
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External asynchronous wait control.
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Configurable size at reset for boot memory bank using external control pins.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
| SPEAR-09-H022_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC |
| SPEAR-09-H042 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head200, ARM 926, 200 K customizable eASIC⑩ gates, large IP portfolio SoC |
| SPEAR-09-H122 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
| SPEAR-09-H122_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
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