參數(shù)資料
型號: SPEAR-09-B042
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289
封裝: 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289
文件頁數(shù): 20/66頁
文件大?。?/td> 917K
代理商: SPEAR-09-B042
SPEAR-09-B042
Main blocks
8.5
Ethernet controller
The Ethernet MAC controller provides the following features:
Compliant with the IEEE 802.3-2002 standard
MII interface to the external PHY
Supports 10/100 Mbps data transfer rates
Local FIFO available (4 Kbyte RX, 2 Kbyte TX)
Supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided for, as well as packet bursting and frame extension at
100 Mbps
Programmable frame length to support both standard and jumbo ethernet frames with
size up to 16 Kbyte
A variety of flexible addresses filtering modes are supported
A set of control and status registers (CSRs) to control GMAC core operation
Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit
data transfers
DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
An AHB slave acting as programming interface to access all CSRs, for both DMA and
GMAC core subsystems
An AHB master for data transfer to system memory
32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions
8.6
USB2 host controller
SPEAr BASIC has two fully independent USB 2.0 hosts and each one is constituted with 5
major blocks:
EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)
OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)
Local 2-Kbyte FIFO
Local DMA
Integrated USB2 transceiver (PHY)
Both hosts can manage an external power switch, providing a control line to enable or
disable the power, and an input line to sense any over-current condition detected by the
external switch.
One host controller at time can perform high speed transfer.
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