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參數(shù)資料
| 型號： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁數(shù)： | 17/66頁 |
| 文件大?。?/td> | 917K |
| 代理商： | SPEAR-09-B042 |
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Main blocks
SPEAR-09-B042
8.2
Clock and reset system
The clock system is a fully programmable block that generates all the clocks necessary to
the chip.
The default operating clock frequencies are:
●
Clock @ 333 MHz for the CPU. (Note 1)
●
Clock @ 166 MHz for AHB bus and AHB peripherals. (Note 1)
●
Clock @ 83 MHz for, APB bus and APB peripherals. (Note 1)
●
Clock @ 333 MHz for DDR memory interface. (Note 2)
The default values give the maximum allowed clock frequencies. The user can modify the
clock frequencies by programming dedicated registers.
The clock system consists of 2 main parts: a multiclock generator block and two internal
PLLs.
The multiclock generator block, takes a reference signal (which is usually delivered by the
PLL), generates all clocks for the IPs of SPEAr BASIC according to dedicated
programmable registers.
Each PLL, uses an oscillator input of 24 MHz, to generate a clock signal at a frequency
corresponding at the highest of the group. This is the reference signal used by the multiclock
generator block to obtain all the other requested clocks for the group. Its main feature is
electromagnetic interference reduction capability. The user can set up the PLL has a to
modulate the VCO with a triangular wave. The resulting signal has a spectrum (and power)
spread over a small programmable range of frequencies centered on F0 (the VCO
frequency), obtaining minimum electromagnetic emissions. This method replaces all the
other traditional methods of E.M.I. reduction, such as filtering, ferrite beads, chokes, adding
power layers and ground planes to PCBs, metal shielding and so on. This gives the
customer appreciable cost savings.
In sleep mode the SoC runs with the PLL disabled so the available frequency is 24 MHz or a
sub-multiple (/2, /4, /8).
Note:
1
This frequency is based on the PLL1.
2
This frequency is based on the PLL2.
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| SPL505YC264ATT | PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| SPL505YC264BT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
| SPEAR-09-H022_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC |
| SPEAR-09-H042 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head200, ARM 926, 200 K customizable eASIC⑩ gates, large IP portfolio SoC |
| SPEAR-09-H122 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
| SPEAR-09-H122_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
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