- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98141 > SPEAR-09-B042 (STMICROELECTRONICS) 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 PDF資料下載
參數(shù)資料
| 型號： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁數(shù)： | 3/66頁 |
| 文件大?。?/td> | 917K |
| 代理商： | SPEAR-09-B042 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
SPEAR-09-B042
Block diagram
5
Block diagram
Figure 2.
Block diagram
5.1
Core architecture
The SoC internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix as detailed in Figure 2.
The switch matrix structure allows different subsystem dataflows to be executed in parallel
improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. Three different memory paths (two of them shared
with other masters) are reserved for the programmable logic to enhance the user application
throughput. The overall memory bandwidth assigned to each master port can be
programmed and optimized through an internal efficient weighted round-robin arbitration
mechanism.
The internal memory pool is completely configurable to improve the performance of the user
application custom logic.
SPEArBASIC
Configurable Cell Array Subsystem
Common Subsystems
Applic Subsys.
C3
Low Speed Subsystem
Basic Subsystem
HS Subsystem
DMA
(8-chan.)
ROM
(32KB)
Flash
Serial
Multi-layer Interconnection Matrix
SDRAM
Controller
-DDR2
-DDRmob
CPU
1
4
2
5-
23
ARM Subsystem
Tmr
APB
Eth.
Mac
USB2.0
Dev
USB2.0
hub-
2host
A
B
D
Cell Array
(Applic. configurable)
M
1-123
M0
M1
M2
M3
M4
CF
G
E
H
RI-
O
Tmr
1-2
WDG
RTC
Gpio
Sys
Ctr
Misc
3
Uart
SPI
I2C
34
F
P
L
Q
ARM926EJ-S
Cache: 16kI 16kD
Coprocessor i/f
Tcm-I/D I
D
SRAM
16KB
SRAM
16KB
SRAM
16KB
SRAM
16KB
JPEG
(Codec)
RAM
(8KB)
IrDA
Int.
Ctr
ADC
Mt
x
-7
4-12
4
3-12
C
2-12(4)
Mt
x-
8
6
G1
-2
6-78
I
7
8
7
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SPEAR300-2 | 32-BIT, FLASH, 333 MHz, RISC MICROCONTROLLER, PBGA289 |
| SPL505YC264ATT | PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| SPL505YC264BT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| SPL505YC264BT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| SPW08F0D | SINGLE COLOR LED, PURE WHITE, 3.5 mm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
| SPEAR-09-H022_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC |
| SPEAR-09-H042 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head200, ARM 926, 200 K customizable eASIC⑩ gates, large IP portfolio SoC |
| SPEAR-09-H122 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
| SPEAR-09-H122_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。