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參數(shù)資料
| 型號： | SPEAR-09-B042 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, I2C BUS CONTROLLER, PBGA289 |
| 封裝： | 15 X 15 MM, 1.70 MM HEIGHT, ROHS COMPLIANT, LFBGA-289 |
| 文件頁數(shù)： | 44/66頁 |
| 文件大小： | 917K |
| 代理商： | SPEAR-09-B042 |
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SPEAR-09-B042
Standard customization
●
I2S_LRCK in master mode can be adjusted for duration of 8, 16 or 32-bits low or high.
The data width can be smaller than I2S_LRCK width.
●
I2S_DIN receives the data. Data can be 8, 16 or 32-bits wide, and is always stored as
32-bit words. A shift left operation to left-align the data is possible.
●
DOUT transmits the data. Data can be 8, 16 or 32-bits, anyway data must be always
stored in 32-bits wide in the buffer. A shift left operation is possible to left align the data.
The DOUT line can be high impedance when out of the samples bits.
●
CLK signal In master mode can be generated from different sources:
–
ClkR_Osci1: MCLK clock from external MCLK crystal
–
ClkR_Gpio4: external oscillator from PL_CLK4 pin.
–
ClkR_Synt_2: from frequency synthesizer (source is AHB frequency),
–
TDM_CLK: I2S and TDM interfaces use the same clock.
The three first signals can be divided by the I2S_CLK block in order to reach the correct
frequency.
In slave mode, the clock is received on the I2S_CLK pin (same pin used in master or slave
mode).
Two banks are used to exchange the samples with the processor. The number of sample
stored in a buffer is programmable.
When the I2S interface reads and stores the data in one bank, the processor is owner of the
other bank, allowing it to read the received data before writing a buffer to be played.
The processor can compute the data directly in the buffer.
When the two banks are switched, this can generate an interrupt or DMA transfer. When this
event occurs, if the processor has not finished computing the previous input buffer and
storing the new output buffer, the computation is out of real time. The software must check
that operations are done in real time.
To avoid synchronization issues. The MSB of the buffers address can be managed by the
device itself. The processor always accesses the right bank between addresses 0x0000 and
0xFFFF.
9.4.7
SPI_I2C cell
The SPI interface has only one slave select signal, SS0.
The I2C interface does not allow control of several devices with the same address what is
frequent for CODECs.
This IP allows management extension of up to 8 SPI devices, or 8 I2C devices at the same
address (total SPI+I2C devices=8).
Table 17.
I2S interface pins
Pins
Description
I2S_LRCK
Left and right channels synchronization (master/slave)
I2S_CLK
I2S clock (master/slave)
I2S_DIN
I2S input
I2S_DOUT
I2S output (tri-state)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
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| SPEAR-09-H122_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
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