參數(shù)資料
型號： SPAK56F8346FV60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 240 MHz, OTHER DSP, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù)： 86/156頁
文件大?。?/td> 2219K
代理商： SPAK56F8346FV60
Interrupt Vector Table
MOTOROLA
56F8346 Technical Data
35
Preliminary
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority
of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt
priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the
lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Section
5.6.12 for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
4.
“EMI_MODE =1” when EMI_MODE pin is tied to VDD at boot up.
5.
Not accessible in reset configuration since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
6.
Booting from this external address allows prototyping of the internal Boot Flash.
7.
The internal Program Flash is relocated in this mode making it accessible.
Table 4-5 Interrupt Vector Table Contents1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
Reserved for Reset Overlay2
Reserved for COP Reset Overlay2
core
2
3
P:$04
Illegal Instruction
core
3
P:$06
SW Interrupt 3
core
4
3
P:$08
HW Stack Overflow
core
5
3
P:$0A
Misaligned Long Word Access
core
6
1-3
P:$0C
OnCE Step Counter
core
7
1-3
P:$0E
OnCE Breakpoint Unit 0
Reserved
core
9
1-3
P:$12
OnCE Trace Buffer
core
10
1-3
P:$14
OnCE Transmit Register Empty
core
11
1-3
P:$16
OnCE Receive Register Full
Reserved
core
14
2
P:$1C
SW Interrupt 2
core
15
1
P:$1E
SW Interrupt 1
core
16
0
P:$20
SW Interrupt 0
core
17
0-2
P:$22
IRQA
core
18
0-2
P:$24
IRQB
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