參數(shù)資料
型號(hào)： SPAK56F8346FV60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 240 MHz, OTHER DSP, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù)： 10/156頁
文件大?。?/td> 2219K
代理商： SPAK56F8346FV60
107
56F8346 Technical Data
MOTOROLA
Preliminary
6.5.10
I/O Short Address Location Register (SIM_ISALH and
SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address and
the upper address bits are not directly controllable. This register set allows limited control of the full address,
as shown in Figure 6-13.
Note:
If this register is set to something other than the top of memory (EOnCE register space) and
the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers,
and debug functions will be affected.
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISAL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the
new value is three cycles.
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1
Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
1
ISAL[23:22]
Write
RESET
1
111
11
1
Instruction Portion
“Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
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