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參數(shù)資料
| 型號(hào)： | SPAK56F8346FV60 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-BIT, 240 MHz, OTHER DSP, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144 |
| 文件頁(yè)數(shù)： | 102/156頁(yè) |
| 文件大?。?/td> | 2219K |
| 代理商： | SPAK56F8346FV60 |
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Award-Winning Development Environment
MOTOROLA
56F8346 Technical Data
5
Preliminary
The 56F8346 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM.
A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable software
routines that can be used to program the main Program and Data Flash memory areas. Both Program and
Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is
1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or
page erased.
A key application-specific feature of the 56F8346 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12
PWM outputs) to enhance motor control functionality. Complementary operation permits programmable
dead time insertion, distortion correction via current sensing by software, and separate top and bottom
output polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC
and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors),
and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with
sufficient output drive capability to directly drive standard optoisolators. A “smoke-inhibit”, write-once
protection feature for key parameters is also included. A patented PWM waveform distortion correction
circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral
reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to synchronize
the analog-to-digital converters through two channels of Quad Timer C.
The 56F8346 incorporates two Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a timeout value to alert when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This hybrid controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and four Quad Timers. Any of
these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required. A
Flex Controller Area Network interface (CAN Version 2.0 A/B compliant) and an internal interrupt
controller are included on the 56F8346.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools
solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8346 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E
system buses communicate with internal memories, the external memory interface and the IP Bus Bridge.
Table 1-1 lists the internal buses in the 56800E architecture and provides a brief description of their
function. Figure 1-2 shows the peripherals and control blocks connected to the IP Bus Bridge. The figures
do not show the on-board regulator and power and ground signals. They also do not show the multiplexing
between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see
which signals are multiplexed with those of other peripherals.
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