參數(shù)資料
型號： SPAK56F8346FV60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 240 MHz, OTHER DSP, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù)： 38/156頁
文件大?。?/td> 2219K
代理商： SPAK56F8346FV60
132
56F8346 Technical Data
MOTOROLA
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Figure 10-5 Asynchronous Reset Timing
Table 10-18 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1.
In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration
tRA
16T
—
ns
RESET Deassertion to First External Address
Output3
3.
During Power-On Reset, it is possible to use the 56F8346 internal reset stretching circuitry to extend this period to 221T.
tRDA
63T
64T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM
TBD
ns
tIDM - FAST
TBD
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
TBD
ns
tIG - FAST
TBD
IRQA Low to First Valid Interrupt Vector Address
Out recovery from Wait State4
4.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
tIRI
TBD
ns
tIRI -FAST
TBD
IRQA Width Assertion to Recover from Stop
State5
5.
The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
—
ns
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop) from external memory
tIF
—
TBD
ns
tIF - FAST
—
TBD
First Fetch
tRA
tRAZ
tRDA
A0–A15,
D0–D15
RESET
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