參數(shù)資料
型號: SPAK56F8346FV60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 240 MHz, OTHER DSP, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù): 35/156頁
文件大?。?/td> 2219K
代理商: SPAK56F8346FV60
56F8346 Signal Pins
MOTOROLA
56F8346 Technical Data
13
Preliminary
VCAP1
51
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator
enabled), connect each pin to a 2.2
F or greater bypass
capacitor in order to bypass the core logic voltage
regulator, required for proper chip operation. When
OCR_DIS is tied to VDD (regulator disabled), these pins
become VDD_CORE and should be connected to a
regulated 2.5V power supply.
VCAP2
128
VCAP3
83
VCAP4
15
VPP1
125
Input
VPP1 - VPP2 — These pins should be left unconnected as
an open circuit for normal functionality.
VPP2
2
CLKMODE
87
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive
the input clock of the chip. The EXTAL pin should be
grounded.
0 = A crystal or ceramic resonator should be connected
between XTAL and EXTAL.
EXTAL
82
Input
External Crystal Oscillator Input — This input can be
connected to an 8MHz external crystal. Tie this pin low if
XTAL is driven by an external clock source.
XTAL
81
Input/
Output
Chip-driven
Crystal Oscillator Output — This output connects the
internal crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the
input and EXTAL connected to GND.
The input clock can be selected to provide the clock
directly to the core. This input clock can also be selected
as the input clock for the on-chip PLL.
CLKO
3
Output
Tri-Stated
Clock Output — This pin outputs a buffered clock signal.
Using the SIM CLKO Select Register (SIM_CLKOSR), this
pin can be programmed as any of the following: disabled,
CLK_MSTR (system clock), IP Bus clock, oscillator output,
prescaler clock and postscaler clock. Other signals are
also available for test purposes.
See Section 6.5.7 for details.
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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