參數(shù)資料
型號: SPAK56F8346FV60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 240 MHz, OTHER DSP, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù): 67/156頁
文件大?。?/td> 2219K
代理商: SPAK56F8346FV60
18
56F8346 Technical Data
MOTOROLA
Preliminary
PS
(CS0)
(GPIOD8)
46
Output
Tri-stated
Program Memory Select — This signal is actually CS0 in
the EMI, which is programmed at reset for compatibility
with the 56F80x PS signal. PS is asserted low for external
program memory access.
Depending upon the state of the DRV bit in the SEMI bus
control register (BCR), PS is tri-stated when the external
bus is inactive.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
CS0 resets to provide the PS function as defined on the
56F80x devices.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
DS
(CS1)
(GPIOD9)
47
Output
Tri-stated
Data Memory Select — This signal is actually CS1 in the
EMI, which is programmed at reset for compatibility with
the 56F80x DS signal. DS is asserted low for external data
memory access.
Depending upon the state of the DRV bit in the SEMI bus
control register (BCR), DS is tri-stated when the external
bus is inactive.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
GPIOD0
(CS2)
48
Input/
Output
Input
Port D GPIO — These two GPIO pins can be individually
programmed as input or output pins.
Chip Select — CS2 - CS3 may be programmed within the
EMI module to act as chip selects for specific areas of the
external memory map.
Depending upon the state of the DRV bit in the SEMI bus
control register (BCR), CS2 - CS3 is tri-stated when the
external bus is inactive.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
GPIOD1
(CS3)
49
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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