參數(shù)資料
型號(hào): SPAK56F8346FV60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 240 MHz, OTHER DSP, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù): 152/156頁
文件大小: 2219K
代理商: SPAK56F8346FV60
Operating Modes
MOTOROLA
56F8346 Technical Data
95
Preliminary
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various
chip operating modes and take appropriate action. These are:
Reset Mode, which has two submodes:
— Hardware Reset Mode
56800E Core and all peripherals are reset. This occurs when the internal POR is asserted,the
RESET pin is asserted or when the COP timer times out.
— Software Reset Mode
Software reset occurs when a 1 is written into the software RESET (SWRST) bit in the SIM
Control Register (SIM_CONTROL). This reset mode is identical to the H/W RESET mode
except since the EMI_MODE and EXTBOOT pins are ignored at reset, EXTBOOT is ignored,
and the state of the mA bit is conserved.
Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip
operation.
Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals continue to run
except the COP and PWMs. COP is disabled and PWM outputs are optionally switched off to
disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User
Manual for details.
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All
other peripherals continue to run.
Stop Mode
When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down.
Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the
PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no
automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking
the chip up from Stop mode, but is not fully functional in Stop mode.
6.4 Operation Mode Register
Figure 6-1 OMR
See Section 4.2 for detailed information on how the Operating Mode Register (OMR) MA and MB bits
operate in this device. Additional information on the EX bit see Section 4.4. For all other bits see, Section
8.2.1 of the DSP56800E Reference Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym
OMR.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NL
CM
XP
SD
R
SA
EX
0
MB
MA
Type
R/W
RESET
0
000
0
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