參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 96/133頁(yè)
文件大?。?/td> 883K
代理商： PLI9080
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SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 88
Version 0.93
5.3 C BUS MODE PINOUT
Table 5-5. C Bus Mode Interface Pin Description
C Mode Bus
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
ADS#
Address Strobe
1
I/O
TS
12 mA
154
Indicates a valid address and the start of a new bus access. Asserted for
the first clock of a bus access.
BLAST#
Burst Last
1
I/O
TS
8 mA
155
Signal driven by the current local bus master to indicate the last transfer
in a bus access.
BTERM#
Burst Terminate
1
I
146
For processors that burst up to 4 Lwords. If BTERM# is disabled
through the PCI 9080 configuration registers, the PCI 9080 also bursts
up to 4 Lwords. If enabled, the PCI 9080 continues to burst until a
BTERM# input is asserted. BTERM# is a ready input that breaks up a
burst cycle and causes another address cycle to occur. Used in
conjunction with the PCI 9080 programmable wait state generator.
DEN#
Data Enable
1
O
TS
12 mA
145
Used in conjunction with DT/R# to provide control for data transceivers
attached to the local bus.
DT/R#
Data Transmit/Receive
1
O
TS
12 mA
138
Used in conjunction with DEN# to provide control for data transceivers
attached to the local bus. When asserted, the signal indicates the PCI
9080 receives data.
LW/R#
Write/Read
1
I/O
TS
12 mA
137
Asserted low for reads and high for writes.
LLOCK#
Bus Lock
1
I
153
Indicates an atomic operation that may require multiple transactions to
complete. Used by the PCI 9080 for direct local access to the PCI bus.
LA[31:2]
Address Bus
30
I/O
TS
8 mA
136, 135,
133-125,
122-115,
113-106,
103-101
Carries the upper 30 bits of the physical address bus. During bursts,
LA3 and LA2 increment to indicate successive data cycles.
LD[31:0]
Data Bus
32
I/O
TS
8 mA
177-182,
185-192,
194-207, 2-5
Carries 32, 16, or 8 bit data quantities depending on bus width
configuration.
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