參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 91/133頁
文件大小： 883K
代理商： PLI9080
SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 83
Version 0.93
5. PIN DESCRIPTION
5.1 PIN SUMMARY
The tables in this section describe the PCI 9080 pins.
Table 5-1 through Table 5-4 provide pin information
common to all three local bus
modes of operation (that
is, C, J, and S modes):
Power and Ground Pin Description
EEPROM Interface Pin Description
PCI System Bus Interface Pin Description
Local Bus Mode and Processor Independent
Interface Pin Description
The pins in Table 5-5 through Table 5-7 correspond to
the local bus modes of the PCI 9080:
C Bus Mode Interface Pin Description
(32-bit address/32-bit data, nonmultiplexed)
J Bus Mode Interface Pin Description
(32-bit address/32-bit data, multiplexed)
S Bus Mode Interface Pin Description
(32-bit address/16-bit data, multiplexed)
The following pins have internal pull-ups:
ADMODE, BIGEND#, BTERM#, DREQ0#, DREQ1#,
EEDO, EESEL, LINTi#, LLOCK#, LRESETi#, NB#,
PCIVOLT, READYi#, S[2:0], and SHORT#.
The following pins have internal pull-downs:
BREQ, LHOLDA, TEST, USERI, and WAITI#.
For a visual view of the chip pin layout, refer to
Figure 7-3, “9080 PIN OUT (S Mode, J Mode, and
C Mode),”
in
Section
7,
Dimensions.”
“Package
Mechanical
The following abbreviations are used in the tables:
I/O
Input and Output Pin
I
Input Pin Only
O
Output Pin Only
TS
Tri-state Pin
OC
Open Collector Pin
TP
Totem Pole Pin
STS
Sustained Tri-state Pin, driven high
for 1 CLK before float
DTS
Driven Tri-state Pin, driven high
for 1/2 CLK before float
Design Notes: PULL up/down (use 3 k
- 10 k
).
All local bus internal pull-ups go through a 2 k
resistor.
All local bus internal pull-downs go through a 100 k
resistor.
All local tri-state I/O pins should have external pull-ups.
Unspecified pins are not connected.
Note: For PCI Pins, DO NOT pull up or pull down any
pins unless the PCI 9080 is being used in an embedded
design. Refer to the
PCI Local Bus Specification
,
Revision 2.1, page 123.
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