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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 108/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 8
PCI 9080
TIMING DIAGRAMS
PLX Technology, Inc., 1997
Page 100
Version 0.93
8. TIMING DIAGRAMS
The PCI 9080 operates in three modes, selected through mode pins, corresponding to three bus types—C, J, and S.
Timing Diagrams are provided for the three operating modes. For some functions, a timing diagram may only be
provided for one mode of operation. Even though a different mode is used, the timing diagram can be used to determine
functionality.
8.1 LIST OF TIMING DIAGRAMS
Timing Diagram 8-1. Initialization from Serial EEPROM
Timing Diagram 8-2. PCI 9080 Local Bus Arbitration
Timing Diagram 8-3. Local LINTi# Input Asserting PCI Output INTA#
Timing Diagram 8-4. (C and J Modes) PCI RST# Asserting Local Output LRESETo#
Timing Diagram
8-5. (C Mode) Local Bus Write to PCI 9080 Configuration Register
Timing Diagram
8-6. (C Mode) Local Bus Read from PCI 9080 Configuration Register
Timing Diagram 8-7. (C Mode) Local Bus Direct Master Memory Write Cycles to PCI Bus
Timing Diagram 8-8. (C Mode) Local Bus Direct Master Memory Read from PCI Bus
Timing Diagram 8-9. (C Mode) Local Bus Direct Master Locked Read Followed by Write and Release
Timing Diagram 8-10. (C Mode) Direct Slave PCI to Local Burst Read of 5
Timing Diagram 8-11. (C Mode) BREQo and Deadlock
Timing Diagram 8-12. (C Mode) Direct Slave PCI to Local Burst Write
Timing Diagram 8-13. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, BTERM Enabled
Timing Diagram 8-14. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, BTERM Disabled
Timing Diagram 8-15. (C Mode) Direct Slave or DMA Burst Read from Local Bus (1 Wait State)
Timing Diagram 8-16. (C Mode) Burst Read from Local Bus (1 Wait State Programmed)
Timing Diagram 8-17. (C Mode) DMA or Direct Slave 2 Lword Burst Write to 8 Bit Local Bus
Timing Diagram 8-18. (C Mode) PCI 9080 Read of DMA Chaining Parameters from Local Bus
Timing Diagram 8-19. (C Mode) Single Cycle DMA Demand Mode PCI to Local
Timing Diagram 8-20. (C Mode) Multiple Cycle DMA Demand Mode PCI to Local
Timing Diagram 8-21. (J Mode) Local Bus Write to PCI 9080 Configuration Register
Timing Diagram 8-22. (J Mode) Local Bus Read from PCI 9080 Configuration Register
Timing Diagram 8-23. (J Mode) Local Bus Direct Master Locked Read Followed by Write and Release
Timing Diagram 8-24. (J Mode) DMA or Direct Slave Burst Write, BTERM Enabled
Timing Diagram 8-25. (J Mode) DMA or Direct Slave Burst Write, BTERM Disabled
Timing Diagram 8-26. (J Mode) DMA or Direct Slave Burst Read, BTERM Enabled
Timing Diagram 8-27. (J Mode) DMA Burst Write to 32 Bit Local Bus Suspended by BREQ Input
Timing Diagram 8-28. (J Mode) Read of DMA Chaining Parameters from Local Bus
Timing Diagram 8-29. (S Mode) Two Phase Clock Synchronization Using LRESETo#
Timing Diagram 8-30. (S Mode) Local Bus Write to Configuration Register
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