參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 33/133頁(yè)
文件大?。?/td> 883K
代理商： PLI9080
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 25
Version 0.93
3.6.3 DMA Data Transfers
The PCI 9080 DMA controller can be programmed to transfer data from the local bus side to the PCI bus side or from the
PCI bus side to the local bus side. Refer to Figure 3-9 and Figure 3-12 for a description of the operation.
3.6.3.1 Local to PCI Bus DMA Transfer
Local Bus Arbitration:
PCI Bus Arbitration:
Releases control of the PCI bus
whenever the FIFO becomes empty,
the PCI latency timer expires and
PCI GRANT de-asserts, a PCI
Disconnect is received, or a Direct
Local to PCI request is pending.
Rearbitrates for control of the PCI bus
when the preprogrammed number of
entries in the FIFO becomes available,
or after two PCI clocks if a disconnect
was received.
PCI
Arbitration
Local Bus
Arbitration
FIFO
Unload FIFO with
PCI Bus
Write Cycles
Load FIFO with
Local Bus
Read Cycles
GNT# REQ# LHOLDA LHOLD
Chaining Mode Descriptors:
At the start of each block transfer, in
Chaining mode only, loads the DMA
Registers by reading four Lwords
from the address specified in the Next
Descriptor Pointer Register.
Chaining Mode Descriptors:
At the start of each block transfer, in
Chaining mode only, loads the DMA
Registers by reading four Lwords
from the address specified in the Next
Descriptor Pointer Register.
Local Interrupt Generation
(Programmable)
Done
Chaining: Terminal
Count for Current
Descriptor
PCI Interrupt Generation
(Programmable)
Done
Chaining: Terminal
Count for Current
Descriptor
Releases control of the local bus whenever
the FIFO becomes full, terminal count is
reached, the local latency timer expires,
the BREQ input is asserted, or a Direct
PCI to Local Bus request is pending.
Rearbitrates for control of the local bus
when the preprogrammed number of
empty entries in the FIFO becomes
available. If the latency timer has expired,
waits until the pause timer expires.
Figure 3-9. Local to PCI Bus DMA Data Transfer Operation
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