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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 16/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 2
PCI 9080
BUS OPERATION
PLX Technology, Inc., 1997
Page 8
Version 0.93
2.2.2.2.3 Partial Lword Accesses
Lword accesses in which not all byte enables are
asserted are broken into single address and data cycles,
as listed in Table 2-7.
Table 2-7. Partial Lword Accesses
Register Value (PCI 18h)(LOC 98h)
Result
Burst Enable
BTERM Enable
(Number of Transfers)
0
0
Single Cycle (Default)
0
1
Single Cycle
1
0
Burst 4 Lwords at a time
1
1
Continuous Burst Mode
2.2.2.3 Recovery States
In J and S modes, the PCI 9080 inserts one recovery
state between the last data transfer and the next
address cycle.
The PCI 9080 does not support the 80960J feature of
using the READY input to add recovery states. No
additional recovery states are added if the READY input
remains asserted during the last data cycle.
2.2.2.4 Local Bus Read Accesses
For all local bus read accesses, the PCI 9080 reads only
bytes corresponding to byte enables requested by the
PCI initiator.
2.2.2.5 Local Bus Write Accesses
For local bus writes, only the bytes specified by a PCI
bus master or by the DMA controller of the PCI 9080 are
written. Access to an 8- or 16-bit bus results in the PCI
bus Lword being broken into multiple local bus transfers.
For each transfer, the byte enables are encoded as in
the 80960C to provide local address bits [LA1:LA0].
2.2.2.6 Direct
8- and 16-Bit Buses
Slave
Write
Accesses—
A Direct PCI access to an 8- or 16-bit bus results in the
PCI bus Lword being broken into multiple local bus
transfers. For each transfer, the byte enables are
encoded as in the 80960C to provide local address bits
[LA1:LA0].
2.2.2.7 Local Bus Data Parity
There is one data parity pin for each byte lane of the
PCI 9080 data bus (DP[3:0]). Even data parity is
generated for each lane during local bus reads from the
PCI 9080 and during PCI 9080 master writes to the local
bus.
Even data parity is checked during local bus writes to
the PCI 9080 and during PCI 9080 reads from the local
bus. Parity is checked for each byte lane with an
asserted byte enable. PCHK# is asserted in the clock
cycle following the data being checked if a parity error is
detected.
Generation or use of local bus data parity is optional.
The signals on the data parity pins do not effect
operation of the PCI 9080. PCI bus parity checking and
generation is independent of local bus parity checking
and generation.
2.2.2.8 Local Bus Little/Big Endian
The PCI bus is a Little Endian bus (that is, data is long
word aligned to the lowermost byte lane). Byte 0
(address 0) appears in AD[7:0], Byte 1 appears in
AD[15:8], Byte 2 appears in AD[23:16] and Byte 3
appears in AD[31:24].
The PCI 9080 local bus can be programmed to operate
in Big or Little Endian mode. In Big Endian mode, the
PCI 9080 transposes the data byte lanes. Data is
transferred as shown in Table 2-8 through Table 2-11.
2.2.2.8.1 32 Bit Local Bus—Big Endian Mode
Data is long word aligned to the uppermost byte lane.
Byte 0 appears on Local Data [31:24], Byte 1 appears
on Local Data [23:16], Byte 2 appears on Local Data
[15:8] and Byte 3 appears on Local Data [7:0].
2.2.2.8.2 16 Bit Local Bus—Big Endian Mode
For a 16 bit local bus, the PCI 9080 can be programmed
to use the upper or lower word lane. Byte lanes and
burst order are listed in Table 2-8 and Table 2-9.
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