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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 93/133頁 |
| 文件大小： | 883K |
| 代理商： | PLI9080 |
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SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 85
Version 0.93
Table 5-3. PCI System Bus Interface Pin Description
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
AD[31:0]
Address and Data
32
I/O
TS
PCI
32-36, 39-44,
46-47, 76-81,
84-89, 91-97
All multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases. The PCI 9080
supports both read and write bursts.
C/BE[3:0]#
Bus Command and
Byte Enables
4
I/O
TS
PCI
70-73
All multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# defines the bus command. During the data
phase C/BE[3:0]# are used as Byte Enables. Refer to PCI spec for
further detail if needed.
CLK
Clock
1
I
54
Provides timing for all transactions on PCI and is an input to every PCI
device. PCI operates up to 33 MHz.
DEVSEL#
Device Select
1
I/O
STS
PCI
64
When actively driven, indicates the driving device has decoded its
address as the target of the current access. As an input, indicates
whether any device on the bus is selected.
FRAME#
Cycle Frame
1
I/O
STS
PCI
57
Driven by the current master to indicate the beginning and duration of an
access. FRAME# is asserted to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is
negated, the transaction is in the final data phase.
GNT#
Grant
1
I
51
Indicates to the agent that access to the bus is granted. Every master
has its own REQ# and GNT#.
IDSEL
Initialization Device
Select
1
I
63
Used as a chip select during configuration read and write transactions.
INTA#
Interrupt A
1
O
OC
PCI
55
Used to request an interrupt.
IRDY#
Initiator Ready
1
I/O
STS
PCI
61
Indicates the ability of the initiating agent (bus master) to complete the
current data phase of the transaction.
LOCK#
Lock
1
I/O
STS
PCI
69
Indicates an atomic operation that may require multiple transactions to
complete.
PAR
Parity
1
I/O
TS
PCI
74
Even parity across AD[31:0] and C/BE[3:0]#. Parity generation is
required by all PCI agents. PAR is stable and valid one clock after the
address phase. For data phases, PAR is stable and valid one clock after
either IRDY# is asserted on a write transaction or TRDY# is asserted on
a read transaction. Once PAR is valid, it remains valid until one clock
after the completion of the current data phase.
PERR#
Parity Error
1
I/O
STS
PCI
65
The reporting of data parity errors during all PCI transactions, except
during a Special Cycle.
REQ#
Request
1
O
PCI
50
Indicates to the arbiter that this agent needs to use the bus. Every
master has its own GNT# and REQ#.
RST#
Reset
1
I
56
Used to bring PCI-specific registers, sequencers and signals to a
consistent state.
SERR#
Systems Error
1
O
OC
PCI
66
Reports address parity errors, data parity errors on the Special Cycle
command, or any other system error where the result will be
catastrophic.
STOP#
Stop
1
I/O
STS
PCI
62
Indicates the current target is requesting the master to stop the current
transaction.
TRDY#
Target Ready
1
I/O
STS
PCI
58
Indicates the ability of the target agent (selected device) to complete the
current data phase of the transaction.
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