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參數(shù)資料
| 型號(hào)： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 73/133頁 |
| 文件大小： | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 65
Version 0.93
4.4.14 (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap)
Register
Table 4-46. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register
Field
Description
Read
Write
Value after Reset
0
Space 1 Enable. A value of 1 enables decoding of PCI addresses for Direct Slave
access to local space 1. A value of 0 disables decoding. If this bit is set to 0, the PCI
BIOS may not allocate (assign) the base address for Space 0.
Yes
Yes
0
1
Reserved.
Yes
Yes
No
Yes
0
0
3:2
If local space 1 is mapped into memory space, bits are not used. If mapped into
I/O space, bit is included with bits [31:4] for remapping.
31:4
Remap of PCI Address to Local Address Space 1 into a Local Address Space.
The bits in this register remap (replace) the PCI Address bits used in decode as the
Local Address bits.
Yes
Yes
0
4.4.15 (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register
Table 4-47. (LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register
Field
Description
Read
Write
Value after Reset
1:0
Memory Space 1 Local Bus Width. A value of 00 indicates a bus width of 8 bits, a
value of 01 indicates a bus width of 16 bits and a value of 10 or 11 indicates a bus
width of 32 bits.
Yes
Yes
S = 01
J = 11
C = 11
5:2
Memory Space 1 Internal Wait States (data to data; bits 0-15).
Yes
Yes
0
6
Memory Space 1 Ready Input Enable. A value of 1 enables Ready input. A value of 0
disables the Ready input.
Yes
Yes
0
7
Memory Space 1 BTERM Input Enable. A value of 1 enables BTERM input. A value
of 0 disables the BTERM input. If this bit is set to 0, the PCI 9080 bursts
4 Lword maximum at a time.
Yes
Yes
0
8
Memory Space 1 Burst Enable. A value of 1 enables bursting. A value of 0 disables
bursting. If burst is disabled, the local bus performs continuous single cycles for burst
PCI read/write cycles.
Yes
Yes
0
9
Memory Space 1 Prefetch Disable. If mapped into memory space, a 0 enables read
prefetching. A value of 1 disables prefetching. If prefetching is disabled, the PCI 9080
disconnects after each memory read.
Yes
Yes
0
10
Read Prefetch Count Enable. When set to 1 and memory prefetching is enabled, the
PCI 9080 prefetches up to the number of Lwords specified in the prefetch count.
When set to 0, the PCI 9080 ignores the count is ignored and continues prefetching
until terminated by the PCI bus.
Yes
Yes
0
14:11
Prefetch Counter. Number of long words to prefetch during memory read cycles
(0-15).
Yes
Yes
0
31:15
Reserved.
Yes
No
0
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