參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 17/133頁
文件大小： 883K
代理商： PLI9080
SECTION 2
PCI 9080
BUS OPERATION
PLX Technology, Inc., 1997
Page 9
Version 0.93
Table 2-8. Upper Word Lane Transfer
Burst Order
Byte Lane
First Transfer
Byte 0 appears on Local Data [31:24]
Byte 1 appears on Local Data [23:16]
Second Transfer
Byte 2 appears on Local Data [31:24]
Byte 3 appears on Local Data [23:16]
Table 2-9. Lower Word Lane Transfer
Burst Order
Byte Lane
First Transfer
Byte 0 appears on Local Data [15:8]
Byte 1 appears on Local Data [7:0]
Second Transfer
Byte 2 appears on Local Data [15:8]
Byte 3 appears on Local Data [7:0]
2.2.2.8.3 8 Bit Local Bus—Big Endian Mode
For an 8 bit local bus, the PCI 9080 can be programmed
to use the upper or lower byte lane. Byte lanes and burst
order are listed in Table 2-10 and Table 2-11.
Table 2-10. Upper Byte Lane Transfer
Burst Order
Byte Lane
First transfer
Byte 0 appears on Local Data [31:24]
Second transfer
Byte 1 appears on Local Data [31:24]
Third transfer
Byte 2 appears on Local Data [31:24]
Fourth transfer
Byte 3 appears on Local Data [31:24]
Table 2-11. Lower Byte Lane Transfer
Burst Order
Byte Lane
First Transfer
Byte 0 appears on Local Data [7:0]
Second Transfer
Byte 1 appears on Local Data [7:0]
Third Transfer
Byte 2 appears on Local Data [7:0]
Fourth Transfer
Byte 3 appears on Local Data [7:0]
For each of the following transfer types, the PCI 9080
local bus can be independently programmed to operate
in Little Endian or Big Endian mode:
Local bus accesses to PCI 9080 configuration
registers
Direct Slave PCI accesses to Local Address
Space 0
Direct Slave PCI accesses to Local Address
Space 1
Direct Slave PCI accesses to expansion ROM
DMA Channel 0 accesses to the local bus
DMA Channel 1 accesses to the local bus
For local bus configuration accesses, an input pin can
be used to dynamically change the Endian mode.
Note: PCI bus is always Little Endian mode.
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