參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 84/133頁
文件大小： 883K
代理商： PLI9080
SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 76
Version 0.93
4.6.11 (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register
Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register
Field
Description
Read
Write
Value after Reset
0
Channel 0 Enable. A value of 1 enables the channel to transfer data. A value of 0
disables the channel from starting a DMA transfer and if in the process of transferring
data suspend transfer (Pause).
Yes
Yes
0
1
Channel 0 Start. Writing a 1 to this bit causes the channel to start transferring data
if the channel is enabled.
No
Yes/Set
0
2
Channel 0 Abort. Writing a 1 to this bit causes the channel to abort the current
transfer. The channel enable bit must be cleared. The channel complete bit is set when
the abort is complete.
No
Yes/Set
0
3
Writing a 1 to this bit clears Channel 0 interrupts.
No
Yes/Clr
0
4
Channel 0 Done. A value of 1 indicates this channel’s transfer is complete. A value of 0
indicates the channel transfer is not complete.
Yes
No
1
7:5
Reserved.
Yes
No
0
4.6.12 (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register
Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register
Field
Description
Read
Write
Value after Reset
0
Channel 1 Enable. A value of 1 enables the channel to transfer data. A value of 0
disables the channel from starting a DMA transfer and if in the process of transferring
data suspend transfer (Pause).
Yes
Yes
0
1
Channel 1 Start. Writing a 1 to this bit causes the channel to start transferring data if
the channel is enabled.
No
Yes/Set
0
2
Channel 1 Abort. Writing a 1 to this bit causes the channel to abort the current
transfer. The channel enable bit must be cleared. The channel complete bit is set when
the abort is complete.
No
Yes/Set
0
3
Writing a 1 to this bit clears Channel 1 interrupts.
No
Yes/Clr
0
4
Channel 1 Done. A value of 1 indicates this channel’s transfer is complete. A value of 0
indicates the channel transfer is not complete.
Yes
No
1
7:5
Reserved.
Yes
No
0
4.6.13 (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register
Same as Local Arbitration register (LARBR) at address PCI:08h, LOC:88h (Table 4-35, “(LARBR; PCI:08h or ACh,
LOC:88h or 12Ch) Local/DMA Arbitration Register”).
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