參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 116/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 8
PCI 9080
TIMING DIAGRAMS
PLX Technology, Inc., 1997
Page 108
Version 0.93
BUS SIGNALS FOR BACKOFF (PCI9060 C_DSRB.TD) (03/06/95)
ADDR
CMD
BYTE ENABLES
ADDR
D0
D0
D1
D2
DIRECT SLAVE PROCEEDS
DIRECT MASTER READ
DIRECT SLAVE READ
DIRECT MASTER WILL NOT GAIN PCI BUS UNTIL DIRECT SLAVE ACCESS COMPLETES
(GNT# ASSERTED , FRAME# DEASSERTED, IRDY# DEASSERTED)
<-- DIRECT SLAVE- BREQ TIMER STARTS
NO DIRECT MASTER READY
D3
D1
D2
0ns
250ns
500ns
750ns
TITLE
PCI CLK
FRAME#
AD[31:0]
C/BE#
IRDY#
DEVSEL#
TRDY#
REQ#
LCLK
LHOLD
LHOLDA
ADS#
LA[31:2]
LD[31:0]
READYO#
READYI#
BREQO
BREQo timer expires and asserts BREQo --->|
to indicate potential deadlock condition
External logic backs off Direct Master transfer
and asserts LHOLDA to grant the local bus for
a Direct Slave transfer.
LHOLDA causes the PCI 9080 local logic to
abort the local side of the Direct Master Read
Note: For partial deadlock, PCI retry timer
bits [31:28] of the Local Bus Region Descriptor
Register can be used to issue RETRYs to the
PCI Master attempting the Direct Slave access.
At completion of the Direct Slave Transfer, LHOLD
is de-asserted which enables External backoff logic
to restart the Direct Master transfer. If the previous
PCI read access has already started, the read
data is flushed and a new PCI Direct Master read
cycle is started.
Refer to Section 3, “
Functional Description
,”
for a description of DEADLOCK
Timing Diagram 8-11. (C Mode) BREQo and Deadlock
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