參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 13/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 1
PCI 9080
GENERAL DESCRIPTION
PLX Technology, Inc., 1997
Page 5
Version 0.93
1.4 COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080
Table 1-3. Comparison of the PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080
Feature
PCI 9060 rev 3
PCI 9060ES
PCI 9060SD
PCI 9080
Number of DMA Channel(s)
2
0
1
2
Local Address Spaces
2
2
3
3
Direct Master Mode
Yes
Yes
No
Yes
Mailbox Registers
Eight 32 bit
Four 32 bit
Four 32 bit
Eight 32 bit
Doorbell Registers
Two 32 bit
Two 8 bit
Two 8 bit
Two 32 bit
FIFOs
8
4
6
8
FIFO Depth—Direct Slave Write, Direct Master
Write, DMA 0 Read and DMA 0 Write
8 Lwords
(32 bytes)
16 Lwords
(64 bytes)
16 Lwords
(64 bytes)
32 Lwords
(128 bytes)
FIFO Depth —Direct Slave Read, Direct Master
Read, DMA 1 Read and DMA 1 Write
8 Lwords
(32 bytes)
16 Lwords
(64 bytes)
16 Lwords
(64 bytes)
16 Lwords
(64 bytes)
LLOCKo# Pin for Lock Cycles
No
Yes
Yes
Yes
WAITI# Pin for Wait State Generation
No
Yes
Yes
Yes
BPCLKO Pin; Buffered PCI Clock
No
Yes
Yes
Yes
DREQ and DACK Pins for Demand Mode
DMA Support
Yes
No
Yes
(Channel 1 only)
Yes
Register Addresses
—
Identical except
9060ES has no
DMA registers and
Tables 25, 26 and 43
were added
Identical, except
9060SD has one DMA
register and Tables 25
and 26 were added
Identical except 9080
has additional I
O
related registers and
30H, 34H, 40H and
44H were remapped
Pinout
—
Signals deleted:
DREQ0 (PIN 29)
DACK0 (PIN 30)
Input signals added:
WAITI (PIN 6)
BIGEND# (PIN 48)
Output signals added:
BPCLK (PIN 168)
LLOCKo (PIN 7)
Signals deleted:
BREQ0 (PIN 21)
DMPAF# (PIN 8)
DREQ0 (PIN 29)
DACK0 (PIN 30)
BTERMo# (PIN 28)
Input signals added:
WAITI (PIN 6)
BIGEND# (PIN 48)
EOT (PIN 164 in
C MODE, PIN 5 in
J and S modes)
Output signals added:
BPCLK (PIN 168)
LLOCKo (PIN 7)
Signals changed:
PCIVOLT (PIN 170)
EESEL (PIN 175)
Big/Little Endian Conversion
No
Yes
Yes
Yes
Spec. 2.1 Deferred Reads
No
Yes
Yes
Yes
Programmable Prefetch Counter
No
Yes
Yes
Yes
Write and Invalidate Cycle
No
Yes
Yes
Yes
Additional Device and Vendor ID Register
No
Yes
Yes
Yes
I
2
O Messaging Unit
No
No
No
Yes
3.3 V PCI Bus Signaling
No
No
No
Yes
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