參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 29/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 21
Version 0.93
Example 1—
A 1 MB local address space 12300000h
through 123FFFFFh is accessible from the PCI bus at
PCI addresses 78900000h through 789FFFFFh.
a. Local initialization software sets the Range and
Local Base Address Registers as follows:
Range—
FFF00000h (1 MB, decode the
upper 12 PCI address bits)
Local Base Address (remap)—
123XXXXXh
(Local Base Address for PCI to local accesses)
(Bit 0, the Space Enable bit, must be set to 1 to
be recognized by the host)
b. PCI Initialization software writes all ones to the PCI
Base Address, then reads it back again.
The PCI 9080 returns a value FFF00000h. The
PCI software then writes to the PCI Base
Address register
PCI Base Address—
789XXXXXh (PCI Base
Address for access to Local Address space)
For PCI direct access to the local bus, the PCI 9080 has
a 32 Lword (128 byte) write FIFO and a 16 Lword
(64 byte) read FIFO. The FIFOs enable the local bus to
operate independently of the PCI bus. The PCI 9080
can be programmed to return a RETRY response or to
throttle TRDY# for any PCI bus transaction attempting
to write to the PCI 9080 local bus when the FIFO is full.
For PCI read transactions from the PCI 9080 local bus,
the PCI 9080 holds off TRDY# while gathering the local
bus Lword to be returned. For read accesses mapped to
the PCI memory space, the PCI 9080 prefetches up
to 16 Lwords (has continuous prefetch mode) from the
local bus. Unused read data is flushed from the FIFO.
For read accesses mapped to the PCI I/O space, the
PCI 9080 does not prefetch read data. Rather, it breaks
each read of the burst cycle into a single address/data
cycle on the local bus.
The period of time the PCI 9080 holds off TRDY# can
be programmed, Target Retry Timer, in the Local Bus
Region Descriptor register. The PCI 9080 issues a
RETRY to the PCI bus transaction master when the
programmed time period expires. This occurs when the
PCI 9080 cannot gain control of the local bus and return
TRDY# within the programmed time period.
3.5.2.2 Deadlock and BREQo
A deadlock situation can occur when a master on the
PCI bus wants to access the PCI 9080 local bus at the
same time a master on the local PCI 9080 bus wants to
access the PCI bus. Two types of deadlock situations
can occur:
a.
PARTIAL DEADLOCK—
A master on the local bus
is performing a direct bus master access to a PCI
bus device other than the PCI bus device that is
concurrently trying to access the local bus.
b.
FULL DEADLOCK—
A master on the local bus is
performing a direct bus master access to the same
PCI bus device that is concurrently trying to access
the local bus.
This applies only to direct (“pass through”) master and
slave accesses through the PCI 9080. Deadlock will not
occur in transfers through the PCI 9080 DMA controller
or the mailboxes.
For PARTIAL DEADLOCK, the PCI access to the local
bus times out (the Target Retry Timer, which is
programmable
through
the
Description for PCI to Local Accesses Register) and the
PCI 9080 responds with a PCI RETRY. The PCI
specification requires that a PCI master release its
request for the PCI bus (de-asserts REQ#) for a
minimum of two PCI clocks after receiving a RETRY.
This allows the PCI bus arbiter to grant the PCI bus to
the PCI 9080 so that it can complete its direct master
access and free up the local bus. Possible solutions are
described below for cases in which the PCI bus arbiter
does not function as described (PCI bus architecture
dependent), waiting for a time-out is undesirable, or a
FULL DEADLOCK condition exists.
Local
Bus
Region
For FULL DEADLOCK, the only solution is to back off
the local master.
3.5.2.2.1 Backoff
The PCI 9080 contains a pin (BREQo) that indicates a
possible deadlock condition exists. The PCI 9080 starts
the BREQo timer (can be reprogrammed, using the
registers) when it detects the following conditions:
a. A master on the local bus is performing a direct bus
master access to the PCI bus.
b. A master on the PCI bus is trying to access memory
or an I/O device on the local bus and is not gaining
access (that is, has not received LHOLDA).
If the timer expires and the PCI 9080 still has not
received LHOLDA, the PCI 9080 asserts BREQo.
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